Multi-chip Fan-out Wafer-Level Packaging
- Commodity name： Multi-chip Fan-out Wafer-Level Packaging
Keywords:
- Product Description
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Product Introduction:
Fan-out packaging is an advanced packaging technology primarily used to achieve higher density electrical connections by redistributing and connecting the input/output (I/O) pins on a chip to a wider range of external circuits. It offers technical advantages such as high integration, excellent electrical performance, and good thermal management.
Application Areas: Fan-out packaging is widely used in high-end electronic devices, especially in 5G communications, data centers, artificial intelligence processors, automotive electronics, the Internet of Things (IoT), and consumer electronics. Its advantages in these areas mainly lie in improving device performance, reducing power consumption, reducing size, and improving heat dissipation, making it an indispensable packaging solution in modern electronics.
Process Capabilities:
▪ FO size: max 25x50mm
▪ RDL L/S: min 2/2um with fan out，can go down to 0.5um if with Bridge Die intercommenction
▪ RDL layer: up to 4 or 5 layers
▪ Package types：single chip FO、multi-chip FO SiP、2.5D/3D FO、
▪ Metal types：Sputtered Ti/Cu、TiW/Cu , Plated Cu、Ni、SnAg
▪ Solder ball pitch：>0.30mm
Keywords:
Multi-chip Fan-out Wafer-Level Packaging
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