High-density packaging technology has developed rapidly in recent years, bringing new challenges to the failure analysis process. Conventional failure analysis methods are difficult to meet the analysis needs of high-density packaging with complex structures and small linewidths, requiring adjustments and improvements to the analysis methods for specific analysis objects. This paper introduces failure analysis techniques such as X-ray, computed tomography (CT) technology, microprobes, and multi-method combinations, analyzes their principles and advantages applicable to high-density packaging. Combined with two high-density packaging failure analysis cases, the use stages and application methods in the cases are specifically introduced, successfully finding the cause of failure. Finally, the advantages, disadvantages, and applicable scope of each method in high-density packaging failure analysis are summarized.

　　0 Introduction

　　Since the 1980s, high-density microelectronic packaging technology has developed rapidly, greatly improving the density of device-level IC packaging and board-level circuit assembly [1-3]. In recent years, high-density packaging represented by ball grid array (BGA) packaging, small outline package (SOP), chip scale package (CSP), and 3D packaging technologies has developed rapidly [4-5]. Compared with traditional packaging technologies such as quad flat package (QFP), high-density packaging has enormous advantages, such as: A 1.27mm pitch BGA can accommodate 350 input/output (I/O) ports in an area of 25mm side length, far exceeding traditional packaging; CSP packaging has a solder ball pitch of less than 1mm, which helps to reduce the overall chip size [6-8]. However, as the feature size of the package gradually decreases, higher requirements are placed on its reliability, and new problems such as metal migration short circuits in high-density wiring, micro-copper pillar bump failure, and BGA solder ball welding have also emerged [9].

　　Failure analysis plays an important role in the integrated circuit industry. Generally, according to the failure mode and phenomenon, the failure mechanism is explored through non-destructive and destructive experimental analysis and verification [10-11]. Traditional failure analysis methods include: external visual inspection, X-ray inspection, ultrasonic scanning inspection, electrical testing, and decapsulation inspection. Due to the characteristics of high-density packaging, such as small linewidth size, high packaging density, and complex structure, traditional failure analysis methods are prone to problems such as inability to detect failure points and destruction of failure points [12-13]. This paper introduces four failure analysis and detection technologies and methods applied to high-density packaging, and details the analysis process with examples.

　　1 Key Technologies and Methods for Failure Analysis of High-Density Packaging

　　1.1 X-ray Detection Technology

　　X-ray detection is an important non-destructive testing technology. When X-rays penetrate different parts of an object, due to differences in material and thickness, different attenuations will occur on different paths, and then the internal characteristics of the object will be presented by detecting the degree of attenuation [14-15].

　　Currently, mainstream X-ray imaging technology uses real-time imaging inspection systems, the main characteristics of which are high resolution and large dynamic range. In addition, with the application of micro-focus detection and other technologies, the accuracy of X-ray detection is constantly improving. For example, the Y.CougarSMT X-ray detector produced by YXLON company has an accuracy of up to 1μm, making it play an important role in the detection of high-density packaging products.

　　1.2 CT Detection Technology

　　Computed tomography (CT) technology is an extension of X-ray imaging technology. It collects X-ray projection information from different angles of the object to be measured and uses a high-performance computer to generate tomographic images and three-dimensional (3D) images [16]. Among them, tomographic scanning imaging can select any cross-section in the XY, YZ, and XZ directions of the sample to be imaged without displaying other irrelevant parts, avoiding imaging interference. 3D imaging uses a computer to perform 3D reconstruction of selectively filtered structures or materials, which is beneficial for analyzing complex structures in high-density packaging. Figure 1 shows a CT detection image of an integrated circuit chip, where Figures 1(a)-(c) are two-dimensional (2D) cross-sectional images of a certain layer, and Figure 1(d) is a 3D composite image.

　　1.3 Combined Use of X-ray Two-Dimensional Imaging and CT Technology

　　X-rays propagate linearly inside the sample, with the advantages of accurate imaging and high resolution. However, for devices with complex structures, the projections of multiple layers will overlap; the thick shells of ceramic or metal packaged electronic components will also reduce the contrast of detail features, affecting the analysis results [17]. CT imaging is reconstructed by computer calculation, and its resolution is slightly lower than that of direct X-ray projection imaging, especially when observing at high magnification, the image quality is lower than that of X-ray 2D imaging, as shown in Figure 2. Figure 2(a) is a 2D magnified X-ray image of a multi-layer printed circuit board (PCB) of a certain device. The metal wire contours are clear and the resolution is high, but irrelevant elements such as BGA solder balls (black circular arrays in the figure) are also photographed. Figure 2(b) is a CT tomographic image of the same part, filtering out irrelevant components such as BGA solder balls, but the resolution is lower. In addition, 3D imaging is also affected by factors such as manual adjustment of the filter window, calculation errors, and acquisition interference. The combined use of X-ray 2D imaging, CT tomographic imaging, and CT 3D imaging technology, using the advantages of the three, adopts different analysis methods for different parts of the device, and uses multiple analysis methods to check the same part from different angles, which can greatly improve the accuracy of the analysis.

　　1.4 Combined Use of Grinding Sample Preparation Technology, X-ray, FIB, and Probe Station

　　Grinding sample preparation technology is a technology that embeds the sample in resin and obtains the true cross-sectional morphology of the sample through a series of grinding processes. It is a destructive analysis and plays an important role in the failure analysis of components. Focused ion beam (FIB) equipment can use high-energy ions to peel off atoms on the sample surface for micro-nano processing. The probe station is an important equipment in the wafer testing field. Probes can be divided into soft needles and hard needles. The tip diameter of soft needles is 0.2-1μm, and the tip diameter of hard needles is mostly 5μm to hundreds of micrometers; the linear movement accuracy of the probe station in the X, Y, and Z directions can be less than 1μm. The probe station has the advantages of high flexibility, high precision, and stable signal [18].

　　In high-density packaging, the metal linewidth is reduced, and the size of some defects is also reduced, even only tens of micrometers. This requires high precision in sample preparation and strict control of the grinding speed. Slight errors may cause excessive grinding. At this time, X-ray observation can be used during grinding to measure the grinding length between two observations before and after grinding for a certain time to calculate the grinding speed under this grinding condition; at the same time, X-ray is used to measure the remaining distance from the grinding surface to the defect, combined with the grinding speed to achieve precise grinding control. Specific grinding conditions were used to grind a high-density packaging failure sample for 30s, and X-ray irradiation was performed before and after grinding to obtain a comparison image, as shown in Figure 3. After measurement, the distances from the grinding surface to the target position were 963 and 585μm, respectively, so the grinding distance was 378μm, and the grinding speed under this condition was 12.6μm/s. Therefore, under this condition, grinding for about 46s more can reach the target position.

　　When polishing to the observation surface, if the defect size is much smaller than the metal linewidth, the effect of metal stretching caused by polishing cannot be ignored. At this time, FIB equipment can be used to remove the surface stretched metal to reveal the true morphology of the underlying metal. If a micro-break point in the middle of a certain circuit is obtained by polishing, and partial circuit electrical testing needs to be performed, a probe station can be used to establish a precise and stable electrical connection. For example: the diameter of a bonding wire fracture (Figure 4(a)) obtained by polishing sample preparation is about 35μm, and conventional electrical connection needles cannot be precisely connected, while the probe station's probe hard needle tip diameter can reach 5μm, and stable connection is achieved through precise positioning, as shown in Figure 4(b).

　　2. Application of Failure Analysis in High-Density Packaging Failure Cases

　　2.1 CPU Failure Analysis

　　A batch of imported CPU products experienced functional failure, with a failure rate of 10-3. The chip is a BGA package with more than 1000 chip pins and 868 package pins, Cu bonding wires, and a 4-layer FR4 printed circuit board. The importer does not provide the correspondence between the chip pins and the package pins.

　　The input/output pins of the package are sequentially tested against the ground pins using forward and reverse I-V testing. It was found that the I-V curves of seven input/output pins were abnormal, showing that the same pin would randomly appear in open circuit and normal conditions in multiple tests. The pressure applied to the chip during testing affects the probability of the two curves appearing. When the pressure is high, it mostly appears normal, and when the pressure is low, it mostly appears open circuit. It is preliminarily judged that there is a loose connection inside the device.

　　X-ray 2D imaging, CT tomography imaging, and CT 3D imaging technologies are used together to inspect and analyze the failed parts. First, CT is used to obtain tomographic images parallel to the chip surface, and layer-by-layer analysis is performed. In areas where some metal linewidths are too small, combined with X-ray 2D images, the connection correspondence between the package pins, metal lead frame, bonding wires, and chip pins is determined for subsequent destructive electrical testing and analysis, as shown in Figure 5. In the figure, H1, H2, J1, L1, L2, M1, M2 are the names of the failed pins, and the inset in Figure 5(b) is a 3D image.

　　Secondly, CT is used to check for abnormalities in metal wiring and vias on cross-sectional images parallel and perpendicular to the chip, as shown in Figure 6. After preliminary inspection, no obvious abnormalities such as open circuits or short circuits were found in the package metal wiring corresponding to the failed pins. It is inferred that the failure point may be located at the first or second bonding point of the bonding wire.

　　The failure point is subjected to longitudinal polishing sample preparation from the outside to the inside. No abnormalities were found at the second bonding point, but abnormalities were found at the first bonding point. After obtaining the cross-section of the first bonding point failure, in order to eliminate the influence of metal stretching during the polishing process, the surface layer of the cross-section is removed using FIB to reveal the original morphology of the deep cross-section, as shown in Figure 7. The insets are all cross-sectional metallographic micrographs. The results show that there is a gap between the Cu bonding wire and the Al pin of the failed pin, with a maximum width of 959nm and a minimum width of 274nm. This gap is the cause of the open-circuit loose connection failure.

　　2.2 Failure Analysis of BGA-Packaged ARM Chips

　　An imported BGA-packaged ARM chip experienced functional abnormalities during use, with a failure rate of approximately 6×10-4, and the chip is Cu-bonded. After desoldering the chip, the functional pins of the failed chip and the reference chip are first tested against the ground pins using I-V testing. It was found that the I-V curve of the abnormal pin was different from that of the reference part, and both the positive and negative currents were reduced, suspected to be caused by an increase in resistance somewhere. X-ray and CT inspection of the chip did not reveal any abnormalities, but since the failure phenomenon was not an open-circuit failure, the X-ray detection accuracy may not meet the requirements, so the dichotomy method is used for electrical localization, and X-ray and CT technologies are also used together to determine the internal connection relationship of the package.

　　Since other package pins show normal curves when tested against the same ground pin, the abnormal point appears in the area of the failed pin-metal wiring-bonding wire-chip. As shown in Figure 8 (the inset is an image of the B, C, and D regions after sample polishing), point A in the figure is the failed pin, point B is the metal lead frame exposed by laser grooving, point C is the first break of the bonding wire after polishing, point D is the second break of the bonding wire after polishing, and point E is the ground pin. First, laser grooving is performed on the metal lead frame area between the bonding wire and the failed pin to expose the metal lead frame. The resistance between point B and the failed pin is tested using a probe station, showing no abnormalities, while the I-V curve between point B and the ground pin is abnormal. Then, polishing is performed downward from the sample surface along a direction parallel to the sample surface to break the middle of the bonding wire without damaging the rest, exposing points C and D. Using a probe station to connect the break points, electrical testing revealed that: there was no abnormality in the resistance between A and C, and the test between D and the ground pin was abnormal. This indicates that the abnormal point is at the first bonding point of the bonding wire corresponding to the failed pin, ruling out abnormalities at the second bonding point.

　　The chip is opened from the front. First, laser is used for preliminary opening, and then weak cold acid is used for opening, maximizing the preservation of the Cu bonding integrity. The bonding wire is pulled out, and the bonding wire breaks at the point where it is bonded to the Al pin, resulting in a fracture. The same method is used to obtain the fracture of the first bonding point of the bonding wire of the comparison device. A scanning electron microscope (SEM) is used to observe and compare the morphology of the typical fractures of the first bonding point of the two devices, and the results are shown in Figure 9. An energy dispersive X-ray spectrometer (EDX) of the SEM equipment is used for component analysis of the fracture, and the results are shown in Figure 10.

　　Combining Figures 9 and 10, it can be found that the morphology and elemental characteristics of the typical fracture area of the failed sample bonding wire are: the large area of the fracture is Cu, and a small part shows the ductile fracture morphology of the two bonded metals separating, and there is Al residue. At the typical fracture of the comparison part, there is a large area of Al pin detachment residue and a titanium barrier layer. The rest of the parts without detached Al pin residue all show the ductile fracture morphology of the two bonded metals separating, and there is Al component residue. Comparative detection experiments show that a good intermetallic compound was not formed between the Cu bonding wire and the Al pin at the first bonding point of the failed part, resulting in an increase in contact resistance and thus failure.

　　Various failure analysis methods have their own advantages and disadvantages in the failure analysis of high-density packaged devices, see Table 1 for details. In certain cases, traditional methods should not be simply followed, and innovations can be made based on sample characteristics, or multiple methods can be used in combination.

　　3 Conclusion

　　Analyzing high-density packaged devices using conventional failure analysis methods can be challenging due to their complex structures and extremely small linewidths. Therefore, it's necessary to innovate traditional failure analysis methods or combine multiple methods. For example, this article demonstrates the application of innovative methods such as bond wire fracture electrical connection testing and high-precision polishing methods assisted by X-ray measurement in the failure analysis of high-density packaged devices, showcasing their effectiveness and highlighting the advantages and disadvantages of traditional failure analysis methods in this context.

　　Microelectronic packaging technology is an extension of microelectronic manufacturing technology. With the miniaturization of integrated circuits, discrete packaging is evolving towards system-in-package, and high-density packaging technology will continue to advance. Conventional failure analysis techniques still require continuous improvement or innovation to address the failure issues of higher-density packaging.

　　Original: Liu Xiaoyu, Chen Yan, et al. Home of Semiconductor Packaging Engineers

　　Semiconductor engineer, semiconductor industry dynamics, semiconductor experience sharing, semiconductor achievement exchange, semiconductor information release. Semiconductor training/conferences/activities, semiconductor community, career planning for semiconductor professionals, and the growth path of chip engineers. 241 original articles.

　　Author: Zhao Gongxin, Guoruan Testing

　　Link: https://xueqiu.com/8421399706/322185429?md5__1038=n4AxyD2DBDu7G%3DDODgDBqDTPOYQi%3DzKKHeH3Y84D

　　Source: Xueqiu

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